OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 44

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4018d 00h /sdr_ctrl/trunk/verif/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4018d 02h /sdr_ctrl/trunk/verif/
39 Test Bench upgradation with bigger data burst size dinesha 4018d 20h /sdr_ctrl/trunk/verif/
38 Port Name clean up dinesha 4020d 01h /sdr_ctrl/trunk/verif/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4020d 03h /sdr_ctrl/trunk/verif/
33 clean up dinesha 4020d 20h /sdr_ctrl/trunk/verif/
32 Debug is enable through +define dinesha 4022d 19h /sdr_ctrl/trunk/verif/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4022d 19h /sdr_ctrl/trunk/verif/
29 SDRAM top and core related run file list are added into svn dinesha 4022d 19h /sdr_ctrl/trunk/verif/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4022d 19h /sdr_ctrl/trunk/verif/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4023d 18h /sdr_ctrl/trunk/verif/
26 invalid log files are removed dinesha 4023d 18h /sdr_ctrl/trunk/verif/
25 tb.sv is renamed as tb_top dinesha 4023d 18h /sdr_ctrl/trunk/verif/
24 Clean Up dinesha 4023d 18h /sdr_ctrl/trunk/verif/
22 Pad sdram clock added dinesha 4024d 23h /sdr_ctrl/trunk/verif/
21 Clean up dinesha 4024d 23h /sdr_ctrl/trunk/verif/
20 8 Bit SDARM support is added dinesha 4026d 18h /sdr_ctrl/trunk/verif/
19 8 Bit SDRAM Support added dinesha 4026d 18h /sdr_ctrl/trunk/verif/
18 8 Bit SDRAM Support is added dinesha 4026d 18h /sdr_ctrl/trunk/verif/
17 micron 8 bit memory models are added into svn dinesha 4026d 18h /sdr_ctrl/trunk/verif/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.