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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 45


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Rev Log message Author Age Path
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4545d 14h /sdr_ctrl/trunk/verif/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4547d 13h /sdr_ctrl/trunk/verif/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4547d 14h /sdr_ctrl/trunk/verif/
39 Test Bench upgradation with bigger data burst size dinesha 4548d 09h /sdr_ctrl/trunk/verif/
38 Port Name clean up dinesha 4549d 14h /sdr_ctrl/trunk/verif/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4549d 16h /sdr_ctrl/trunk/verif/
33 clean up dinesha 4550d 09h /sdr_ctrl/trunk/verif/
32 Debug is enable through +define dinesha 4552d 08h /sdr_ctrl/trunk/verif/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4552d 08h /sdr_ctrl/trunk/verif/
29 SDRAM top and core related run file list are added into svn dinesha 4552d 08h /sdr_ctrl/trunk/verif/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4552d 08h /sdr_ctrl/trunk/verif/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4553d 06h /sdr_ctrl/trunk/verif/
26 invalid log files are removed dinesha 4553d 06h /sdr_ctrl/trunk/verif/
25 is renamed as tb_top dinesha 4553d 06h /sdr_ctrl/trunk/verif/
24 Clean Up dinesha 4553d 07h /sdr_ctrl/trunk/verif/
22 Pad sdram clock added dinesha 4554d 12h /sdr_ctrl/trunk/verif/
21 Clean up dinesha 4554d 12h /sdr_ctrl/trunk/verif/
20 8 Bit SDARM support is added dinesha 4556d 07h /sdr_ctrl/trunk/verif/
19 8 Bit SDRAM Support added dinesha 4556d 07h /sdr_ctrl/trunk/verif/
18 8 Bit SDRAM Support is added dinesha 4556d 07h /sdr_ctrl/trunk/verif/

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