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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 68

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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4031d 23h /sdr_ctrl/trunk/verif/
65 Updated Log file with CAS latency support 4,5 dinesha 4350d 06h /sdr_ctrl/trunk/verif/
56 FPGA Synth optimisation dinesha 4469d 21h /sdr_ctrl/trunk/verif/
53 Test bench upgradation dinesha 4473d 20h /sdr_ctrl/trunk/verif/
49 clean up dinesha 4476d 23h /sdr_ctrl/trunk/verif/
48 top-level cleanup dinesha 4476d 23h /sdr_ctrl/trunk/verif/
46 test bench upgrade + rtl cleanup dinesha 4479d 00h /sdr_ctrl/trunk/verif/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4479d 04h /sdr_ctrl/trunk/verif/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4481d 02h /sdr_ctrl/trunk/verif/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4481d 04h /sdr_ctrl/trunk/verif/
39 Test Bench upgradation with bigger data burst size dinesha 4481d 23h /sdr_ctrl/trunk/verif/
38 Port Name clean up dinesha 4483d 04h /sdr_ctrl/trunk/verif/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4483d 05h /sdr_ctrl/trunk/verif/
33 clean up dinesha 4483d 22h /sdr_ctrl/trunk/verif/
32 Debug is enable through +define dinesha 4485d 21h /sdr_ctrl/trunk/verif/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4485d 22h /sdr_ctrl/trunk/verif/
29 SDRAM top and core related run file list are added into svn dinesha 4485d 22h /sdr_ctrl/trunk/verif/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4485d 22h /sdr_ctrl/trunk/verif/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4486d 20h /sdr_ctrl/trunk/verif/
26 invalid log files are removed dinesha 4486d 20h /sdr_ctrl/trunk/verif/

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