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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1051d 01h /sdr_ctrl/trunk/verif/log/
65 Updated Log file with CAS latency support 4,5 dinesha 4414d 10h /sdr_ctrl/trunk/verif/log/
56 FPGA Synth optimisation dinesha 4534d 01h /sdr_ctrl/trunk/verif/log/
53 Test bench upgradation dinesha 4538d 00h /sdr_ctrl/trunk/verif/log/
49 clean up dinesha 4541d 03h /sdr_ctrl/trunk/verif/log/
48 top-level cleanup dinesha 4541d 03h /sdr_ctrl/trunk/verif/log/
46 test bench upgrade + rtl cleanup dinesha 4543d 04h /sdr_ctrl/trunk/verif/log/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4543d 08h /sdr_ctrl/trunk/verif/log/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4545d 06h /sdr_ctrl/trunk/verif/log/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4545d 08h /sdr_ctrl/trunk/verif/log/
39 Test Bench upgradation with bigger data burst size dinesha 4546d 03h /sdr_ctrl/trunk/verif/log/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4547d 09h /sdr_ctrl/trunk/verif/log/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4550d 02h /sdr_ctrl/trunk/verif/log/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4551d 00h /sdr_ctrl/trunk/verif/log/
26 invalid log files are removed dinesha 4551d 00h /sdr_ctrl/trunk/verif/log/
21 Clean up dinesha 4552d 05h /sdr_ctrl/trunk/verif/log/
20 8 Bit SDARM support is added dinesha 4554d 00h /sdr_ctrl/trunk/verif/log/
6 Golden Log files are added into SVN dinesha 4561d 02h /sdr_ctrl/trunk/verif/log/
2 dinesha 4571d 02h /sdr_ctrl/trunk/verif/log/

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