URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 42

Rev	Log message	Author	Age	Path
39	Test Bench upgradation with bigger data burst size	dinesha	4476d 08h	/sdr_ctrl/trunk/verif/log/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4477d 15h	/sdr_ctrl/trunk/verif/log/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4480d 07h	/sdr_ctrl/trunk/verif/log/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4481d 05h	/sdr_ctrl/trunk/verif/log/
26	invalid log files are removed	dinesha	4481d 05h	/sdr_ctrl/trunk/verif/log/
21	Clean up	dinesha	4482d 11h	/sdr_ctrl/trunk/verif/log/
20	8 Bit SDARM support is added	dinesha	4484d 05h	/sdr_ctrl/trunk/verif/log/
6	Golden Log files are added into SVN	dinesha	4491d 07h	/sdr_ctrl/trunk/verif/log/
2		dinesha	4501d 07h	/sdr_ctrl/trunk/verif/log/