Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] - Rev 44


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4021d 22h /sdr_ctrl/trunk/verif/log/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4022d 00h /sdr_ctrl/trunk/verif/log/
39 Test Bench upgradation with bigger data burst size dinesha 4022d 19h /sdr_ctrl/trunk/verif/log/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4024d 01h /sdr_ctrl/trunk/verif/log/
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4026d 18h /sdr_ctrl/trunk/verif/log/
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4027d 16h /sdr_ctrl/trunk/verif/log/
26 invalid log files are removed dinesha 4027d 16h /sdr_ctrl/trunk/verif/log/
21 Clean up dinesha 4028d 21h /sdr_ctrl/trunk/verif/log/
20 8 Bit SDARM support is added dinesha 4030d 16h /sdr_ctrl/trunk/verif/log/
6 Golden Log files are added into SVN dinesha 4037d 18h /sdr_ctrl/trunk/verif/log/
2 dinesha 4047d 18h /sdr_ctrl/trunk/verif/log/

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.