OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_32BIT_complie.log] - Rev 73

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 355d 00h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log
65 Updated Log file with CAS latency support 4,5 dinesha 3718d 08h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 3854d 22h /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.