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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_8BIT_basic_test1.log] - Rev 53

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Rev Log message Author Age Path
53 Test bench upgradation dinesha 4520d 07h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
49 clean up dinesha 4523d 10h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
48 top-level cleanup dinesha 4523d 11h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
46 test bench upgrade + rtl cleanup dinesha 4525d 11h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4525d 16h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4527d 15h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4532d 09h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4533d 07h /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log

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