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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_16BIT_basic_test1.log] - Rev 73


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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 354d 23h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
65 Updated Log file with CAS latency support 4,5 dinesha 3718d 08h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
56 FPGA Synth optimisation dinesha 3838d 00h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
53 Test bench upgradation dinesha 3841d 22h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
48 top-level cleanup dinesha 3845d 01h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
46 test bench upgrade + rtl cleanup dinesha 3847d 02h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 3847d 06h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3849d 04h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3849d 06h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
39 Test Bench upgradation with bigger data burst size dinesha 3850d 01h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3851d 08h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 3854d 00h /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log

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