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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr16_sim.log] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3960d 02h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3960d 03h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 3960d 22h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3962d 05h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 3964d 21h /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log

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