Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr32_sim.log] - Rev 53


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 Test bench upgradation dinesha 4515d 20h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
48 top-level cleanup dinesha 4519d 00h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
46 test bench upgrade + rtl cleanup dinesha 4521d 00h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4521d 05h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4523d 04h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 4523d 23h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4525d 06h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4527d 22h /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.