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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr8_sim.log] - Rev 65


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Rev Log message Author Age Path
65 Updated Log file with CAS latency support 4,5 dinesha 4392d 09h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
56 FPGA Synth optimisation dinesha 4512d 00h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
53 Test bench upgradation dinesha 4515d 23h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
48 top-level cleanup dinesha 4519d 02h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
46 test bench upgrade + rtl cleanup dinesha 4521d 03h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4521d 07h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4523d 05h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4523d 07h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 4524d 02h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4525d 08h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4528d 01h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log

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