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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr8_sim.log] - Rev 43


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Rev Log message Author Age Path
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4526d 06h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
39 Test Bench upgradation with bigger data burst size dinesha 4527d 00h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4528d 07h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4530d 23h /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log

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