URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run] - Rev 72

Rev	Log message	Author	Age	Path
72	Command Clean up for model-sim mode	dinesha	3972d 21h	/sdr_ctrl/trunk/verif/run
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4471d 19h	/sdr_ctrl/trunk/verif/run
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4473d 19h	/sdr_ctrl/trunk/verif/run
33	clean up	dinesha	4476d 14h	/sdr_ctrl/trunk/verif/run
29	SDRAM top and core related run file list are added into svn	dinesha	4478d 13h	/sdr_ctrl/trunk/verif/run
19	8 Bit SDRAM Support added	dinesha	4482d 11h	/sdr_ctrl/trunk/verif/run
5	Run files are updated into SVN	dinesha	4489d 14h	/sdr_ctrl/trunk/verif/run
2		dinesha	4499d 13h	/sdr_ctrl/trunk/verif/run