URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 42

Rev	Log message	Author	Age	Path
39	Test Bench upgradation with bigger data burst size	dinesha	4476d 00h	/sdr_ctrl/trunk/verif/tb/
38	Port Name clean up	dinesha	4477d 05h	/sdr_ctrl/trunk/verif/tb/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4477d 07h	/sdr_ctrl/trunk/verif/tb/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4479d 23h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	4480d 21h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	4480d 21h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	4482d 02h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	4483d 21h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	4486d 22h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	4486d 23h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	4490d 23h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	4500d 23h	/sdr_ctrl/trunk/verif/tb/