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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3960d 02h /sdr_ctrl/trunk/verif/tb/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3960d 03h /sdr_ctrl/trunk/verif/tb/
39 Test Bench upgradation with bigger data burst size dinesha 3960d 22h /sdr_ctrl/trunk/verif/tb/
38 Port Name clean up dinesha 3962d 03h /sdr_ctrl/trunk/verif/tb/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 3962d 05h /sdr_ctrl/trunk/verif/tb/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3964d 21h /sdr_ctrl/trunk/verif/tb/
25 tb.sv is renamed as tb_top dinesha 3965d 20h /sdr_ctrl/trunk/verif/tb/
24 Clean Up dinesha 3965d 20h /sdr_ctrl/trunk/verif/tb/
22 Pad sdram clock added dinesha 3967d 01h /sdr_ctrl/trunk/verif/tb/
18 8 Bit SDRAM Support is added dinesha 3968d 20h /sdr_ctrl/trunk/verif/tb/
14 Unnecessary device config are removed dinesha 3971d 21h /sdr_ctrl/trunk/verif/tb/
12 Column Bits are made programmable dinesha 3971d 21h /sdr_ctrl/trunk/verif/tb/
8 test bench files are added into SVN dinesha 3975d 22h /sdr_ctrl/trunk/verif/tb/
2 dinesha 3985d 21h /sdr_ctrl/trunk/verif/tb/

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