URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 45

Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	5035d 16h	/sdr_ctrl/trunk/verif/tb/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	5037d 14h	/sdr_ctrl/trunk/verif/tb/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	5037d 15h	/sdr_ctrl/trunk/verif/tb/
39	Test Bench upgradation with bigger data burst size	dinesha	5038d 10h	/sdr_ctrl/trunk/verif/tb/
38	Port Name clean up	dinesha	5039d 15h	/sdr_ctrl/trunk/verif/tb/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	5039d 17h	/sdr_ctrl/trunk/verif/tb/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	5042d 09h	/sdr_ctrl/trunk/verif/tb/
25	tb.sv is renamed as tb_top	dinesha	5043d 08h	/sdr_ctrl/trunk/verif/tb/
24	Clean Up	dinesha	5043d 08h	/sdr_ctrl/trunk/verif/tb/
22	Pad sdram clock added	dinesha	5044d 13h	/sdr_ctrl/trunk/verif/tb/
18	8 Bit SDRAM Support is added	dinesha	5046d 08h	/sdr_ctrl/trunk/verif/tb/
14	Unnecessary device config are removed	dinesha	5049d 09h	/sdr_ctrl/trunk/verif/tb/
12	Column Bits are made programmable	dinesha	5049d 09h	/sdr_ctrl/trunk/verif/tb/
8	test bench files are added into SVN	dinesha	5053d 10h	/sdr_ctrl/trunk/verif/tb/
2		dinesha	5063d 09h	/sdr_ctrl/trunk/verif/tb/