OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 56

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 FPGA Synth optimisation dinesha 4602d 08h /sdr_ctrl/trunk/verif/tb/
53 Test bench upgradation dinesha 4606d 06h /sdr_ctrl/trunk/verif/tb/
49 clean up dinesha 4609d 09h /sdr_ctrl/trunk/verif/tb/
48 top-level cleanup dinesha 4609d 10h /sdr_ctrl/trunk/verif/tb/
46 test bench upgrade + rtl cleanup dinesha 4611d 10h /sdr_ctrl/trunk/verif/tb/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4611d 15h /sdr_ctrl/trunk/verif/tb/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4613d 13h /sdr_ctrl/trunk/verif/tb/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4613d 15h /sdr_ctrl/trunk/verif/tb/
39 Test Bench upgradation with bigger data burst size dinesha 4614d 09h /sdr_ctrl/trunk/verif/tb/
38 Port Name clean up dinesha 4615d 14h /sdr_ctrl/trunk/verif/tb/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4615d 16h /sdr_ctrl/trunk/verif/tb/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4618d 08h /sdr_ctrl/trunk/verif/tb/
25 tb.sv is renamed as tb_top dinesha 4619d 07h /sdr_ctrl/trunk/verif/tb/
24 Clean Up dinesha 4619d 07h /sdr_ctrl/trunk/verif/tb/
22 Pad sdram clock added dinesha 4620d 12h /sdr_ctrl/trunk/verif/tb/
18 8 Bit SDRAM Support is added dinesha 4622d 07h /sdr_ctrl/trunk/verif/tb/
14 Unnecessary device config are removed dinesha 4625d 08h /sdr_ctrl/trunk/verif/tb/
12 Column Bits are made programmable dinesha 4625d 08h /sdr_ctrl/trunk/verif/tb/
8 test bench files are added into SVN dinesha 4629d 09h /sdr_ctrl/trunk/verif/tb/
2 dinesha 4639d 08h /sdr_ctrl/trunk/verif/tb/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.