OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4105d 15h /sdr_ctrl/trunk/verif/tb/
56 FPGA Synth optimisation dinesha 4543d 14h /sdr_ctrl/trunk/verif/tb/
53 Test bench upgradation dinesha 4547d 12h /sdr_ctrl/trunk/verif/tb/
49 clean up dinesha 4550d 15h /sdr_ctrl/trunk/verif/tb/
48 top-level cleanup dinesha 4550d 15h /sdr_ctrl/trunk/verif/tb/
46 test bench upgrade + rtl cleanup dinesha 4552d 16h /sdr_ctrl/trunk/verif/tb/
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4552d 20h /sdr_ctrl/trunk/verif/tb/
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4554d 18h /sdr_ctrl/trunk/verif/tb/
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4554d 20h /sdr_ctrl/trunk/verif/tb/
39 Test Bench upgradation with bigger data burst size dinesha 4555d 15h /sdr_ctrl/trunk/verif/tb/
38 Port Name clean up dinesha 4556d 20h /sdr_ctrl/trunk/verif/tb/
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4556d 22h /sdr_ctrl/trunk/verif/tb/
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4559d 14h /sdr_ctrl/trunk/verif/tb/
25 tb.sv is renamed as tb_top dinesha 4560d 12h /sdr_ctrl/trunk/verif/tb/
24 Clean Up dinesha 4560d 12h /sdr_ctrl/trunk/verif/tb/
22 Pad sdram clock added dinesha 4561d 18h /sdr_ctrl/trunk/verif/tb/
18 8 Bit SDRAM Support is added dinesha 4563d 12h /sdr_ctrl/trunk/verif/tb/
14 Unnecessary device config are removed dinesha 4566d 13h /sdr_ctrl/trunk/verif/tb/
12 Column Bits are made programmable dinesha 4566d 14h /sdr_ctrl/trunk/verif/tb/
8 test bench files are added into SVN dinesha 4570d 14h /sdr_ctrl/trunk/verif/tb/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.