OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 68

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4041d 07h /sdr_ctrl/trunk/verif/tb
56 FPGA Synth optimisation dinesha 4479d 06h /sdr_ctrl/trunk/verif/tb
53 Test bench upgradation dinesha 4483d 04h /sdr_ctrl/trunk/verif/tb
49 clean up dinesha 4486d 07h /sdr_ctrl/trunk/verif/tb
48 top-level cleanup dinesha 4486d 07h /sdr_ctrl/trunk/verif/tb
46 test bench upgrade + rtl cleanup dinesha 4488d 08h /sdr_ctrl/trunk/verif/tb
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4488d 13h /sdr_ctrl/trunk/verif/tb
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4490d 11h /sdr_ctrl/trunk/verif/tb
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4490d 12h /sdr_ctrl/trunk/verif/tb
39 Test Bench upgradation with bigger data burst size dinesha 4491d 07h /sdr_ctrl/trunk/verif/tb
38 Port Name clean up dinesha 4492d 12h /sdr_ctrl/trunk/verif/tb
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4492d 14h /sdr_ctrl/trunk/verif/tb
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4495d 06h /sdr_ctrl/trunk/verif/tb
25 tb.sv is renamed as tb_top dinesha 4496d 05h /sdr_ctrl/trunk/verif/tb
24 Clean Up dinesha 4496d 05h /sdr_ctrl/trunk/verif/tb
22 Pad sdram clock added dinesha 4497d 10h /sdr_ctrl/trunk/verif/tb
18 8 Bit SDRAM Support is added dinesha 4499d 05h /sdr_ctrl/trunk/verif/tb
14 Unnecessary device config are removed dinesha 4502d 06h /sdr_ctrl/trunk/verif/tb
12 Column Bits are made programmable dinesha 4502d 06h /sdr_ctrl/trunk/verif/tb
8 test bench files are added into SVN dinesha 4506d 07h /sdr_ctrl/trunk/verif/tb

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.