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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 3960d 01h /sdr_ctrl/trunk/verif/tb/tb_core.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 3960d 03h /sdr_ctrl/trunk/verif/tb/tb_core.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 3964d 21h /sdr_ctrl/trunk/verif/tb/tb_core.sv

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