URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 39

Rev	Log message	Author	Age	Path
39	Test Bench upgradation with bigger data burst size	dinesha	4476d 13h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
38	Port Name clean up	dinesha	4477d 18h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4477d 20h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4480d 12h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
25	tb.sv is renamed as tb_top	dinesha	4481d 11h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
24	Clean Up	dinesha	4481d 11h	/sdr_ctrl/trunk/verif/tb/tb.sv
22	Pad sdram clock added	dinesha	4482d 16h	/sdr_ctrl/trunk/verif/tb/tb.sv
18	8 Bit SDRAM Support is added	dinesha	4484d 11h	/sdr_ctrl/trunk/verif/tb/tb.sv
14	Unnecessary device config are removed	dinesha	4487d 12h	/sdr_ctrl/trunk/verif/tb/tb.sv
12	Column Bits are made programmable	dinesha	4487d 12h	/sdr_ctrl/trunk/verif/tb/tb.sv
8	test bench files are added into SVN	dinesha	4491d 13h	/sdr_ctrl/trunk/verif/tb/tb.sv