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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 44

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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4522d 13h /sdr_ctrl/trunk/verif/tb/tb_top.sv
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4522d 15h /sdr_ctrl/trunk/verif/tb/tb_top.sv
39 Test Bench upgradation with bigger data burst size dinesha 4523d 09h /sdr_ctrl/trunk/verif/tb/tb_top.sv
38 Port Name clean up dinesha 4524d 14h /sdr_ctrl/trunk/verif/tb/tb_top.sv
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4524d 16h /sdr_ctrl/trunk/verif/tb/tb_top.sv
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4527d 08h /sdr_ctrl/trunk/verif/tb/tb_top.sv
25 tb.sv is renamed as tb_top dinesha 4528d 07h /sdr_ctrl/trunk/verif/tb/tb_top.sv
24 Clean Up dinesha 4528d 07h /sdr_ctrl/trunk/verif/tb/tb.sv
22 Pad sdram clock added dinesha 4529d 12h /sdr_ctrl/trunk/verif/tb/tb.sv
18 8 Bit SDRAM Support is added dinesha 4531d 07h /sdr_ctrl/trunk/verif/tb/tb.sv
14 Unnecessary device config are removed dinesha 4534d 08h /sdr_ctrl/trunk/verif/tb/tb.sv
12 Column Bits are made programmable dinesha 4534d 08h /sdr_ctrl/trunk/verif/tb/tb.sv
8 test bench files are added into SVN dinesha 4538d 09h /sdr_ctrl/trunk/verif/tb/tb.sv

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