URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 44

Rev	Log message	Author	Age	Path
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4466d 21h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4466d 22h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
39	Test Bench upgradation with bigger data burst size	dinesha	4467d 17h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
38	Port Name clean up	dinesha	4468d 22h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4469d 00h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4471d 16h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
25	tb.sv is renamed as tb_top	dinesha	4472d 15h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
24	Clean Up	dinesha	4472d 15h	/sdr_ctrl/trunk/verif/tb/tb.sv
22	Pad sdram clock added	dinesha	4473d 20h	/sdr_ctrl/trunk/verif/tb/tb.sv
18	8 Bit SDRAM Support is added	dinesha	4475d 15h	/sdr_ctrl/trunk/verif/tb/tb.sv
14	Unnecessary device config are removed	dinesha	4478d 16h	/sdr_ctrl/trunk/verif/tb/tb.sv
12	Column Bits are made programmable	dinesha	4478d 16h	/sdr_ctrl/trunk/verif/tb/tb.sv
8	test bench files are added into SVN	dinesha	4482d 17h	/sdr_ctrl/trunk/verif/tb/tb.sv