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[/] [sdr_ctrl/] [trunk/] [verif/] [tb] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1136d 02h /sdr_ctrl/trunk/verif/tb
70 Warning Cleanup dinesha 4181d 03h /sdr_ctrl/trunk/verif/tb
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4181d 04h /sdr_ctrl/trunk/verif/tb
56 FPGA Synth optimisation dinesha 4619d 03h /sdr_ctrl/trunk/verif/tb
53 Test bench upgradation dinesha 4623d 01h /sdr_ctrl/trunk/verif/tb
49 clean up dinesha 4626d 04h /sdr_ctrl/trunk/verif/tb
48 top-level cleanup dinesha 4626d 04h /sdr_ctrl/trunk/verif/tb
46 test bench upgrade + rtl cleanup dinesha 4628d 05h /sdr_ctrl/trunk/verif/tb
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4628d 09h /sdr_ctrl/trunk/verif/tb
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4630d 08h /sdr_ctrl/trunk/verif/tb
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4630d 09h /sdr_ctrl/trunk/verif/tb
39 Test Bench upgradation with bigger data burst size dinesha 4631d 04h /sdr_ctrl/trunk/verif/tb
38 Port Name clean up dinesha 4632d 09h /sdr_ctrl/trunk/verif/tb
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4632d 11h /sdr_ctrl/trunk/verif/tb
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4635d 03h /sdr_ctrl/trunk/verif/tb
25 tb.sv is renamed as tb_top dinesha 4636d 02h /sdr_ctrl/trunk/verif/tb
24 Clean Up dinesha 4636d 02h /sdr_ctrl/trunk/verif/tb
22 Pad sdram clock added dinesha 4637d 07h /sdr_ctrl/trunk/verif/tb
18 8 Bit SDRAM Support is added dinesha 4639d 02h /sdr_ctrl/trunk/verif/tb
14 Unnecessary device config are removed dinesha 4642d 03h /sdr_ctrl/trunk/verif/tb

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