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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [verif/] [tb] - Rev 53

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Rev Log message Author Age Path
53 Test bench upgradation dinesha 4485d 17h /sdr_ctrl/trunk/verif/tb
49 clean up dinesha 4488d 20h /sdr_ctrl/trunk/verif/tb
48 top-level cleanup dinesha 4488d 21h /sdr_ctrl/trunk/verif/tb
46 test bench upgrade + rtl cleanup dinesha 4490d 21h /sdr_ctrl/trunk/verif/tb
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4491d 02h /sdr_ctrl/trunk/verif/tb
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4493d 00h /sdr_ctrl/trunk/verif/tb
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4493d 02h /sdr_ctrl/trunk/verif/tb
39 Test Bench upgradation with bigger data burst size dinesha 4493d 20h /sdr_ctrl/trunk/verif/tb
38 Port Name clean up dinesha 4495d 01h /sdr_ctrl/trunk/verif/tb
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4495d 03h /sdr_ctrl/trunk/verif/tb
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4497d 19h /sdr_ctrl/trunk/verif/tb
25 tb.sv is renamed as tb_top dinesha 4498d 18h /sdr_ctrl/trunk/verif/tb
24 Clean Up dinesha 4498d 18h /sdr_ctrl/trunk/verif/tb
22 Pad sdram clock added dinesha 4499d 23h /sdr_ctrl/trunk/verif/tb
18 8 Bit SDRAM Support is added dinesha 4501d 18h /sdr_ctrl/trunk/verif/tb
14 Unnecessary device config are removed dinesha 4504d 19h /sdr_ctrl/trunk/verif/tb
12 Column Bits are made programmable dinesha 4504d 19h /sdr_ctrl/trunk/verif/tb
8 test bench files are added into SVN dinesha 4508d 20h /sdr_ctrl/trunk/verif/tb
2 dinesha 4518d 19h /sdr_ctrl/trunk/verif/tb

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