OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif] - Rev 73

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1136d 03h /sdr_ctrl/trunk/verif
72 Command Clean up for model-sim mode dinesha 4129d 12h /sdr_ctrl/trunk/verif
70 Warning Cleanup dinesha 4181d 04h /sdr_ctrl/trunk/verif
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4181d 05h /sdr_ctrl/trunk/verif
65 Updated Log file with CAS latency support 4,5 dinesha 4499d 12h /sdr_ctrl/trunk/verif
56 FPGA Synth optimisation dinesha 4619d 04h /sdr_ctrl/trunk/verif
53 Test bench upgradation dinesha 4623d 02h /sdr_ctrl/trunk/verif
49 clean up dinesha 4626d 05h /sdr_ctrl/trunk/verif
48 top-level cleanup dinesha 4626d 05h /sdr_ctrl/trunk/verif
46 test bench upgrade + rtl cleanup dinesha 4628d 06h /sdr_ctrl/trunk/verif
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4628d 10h /sdr_ctrl/trunk/verif
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4630d 09h /sdr_ctrl/trunk/verif
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4630d 10h /sdr_ctrl/trunk/verif
39 Test Bench upgradation with bigger data burst size dinesha 4631d 05h /sdr_ctrl/trunk/verif
38 Port Name clean up dinesha 4632d 10h /sdr_ctrl/trunk/verif
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4632d 12h /sdr_ctrl/trunk/verif
33 clean up dinesha 4633d 05h /sdr_ctrl/trunk/verif
32 Debug is enable through +define dinesha 4635d 04h /sdr_ctrl/trunk/verif
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4635d 04h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4635d 04h /sdr_ctrl/trunk/verif

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.