URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif] - Rev 28

Rev	Log message	Author	Age	Path
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4479d 14h	/sdr_ctrl/trunk/verif
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4480d 12h	/sdr_ctrl/trunk/verif
26	invalid log files are removed	dinesha	4480d 12h	/sdr_ctrl/trunk/verif
25	tb.sv is renamed as tb_top	dinesha	4480d 12h	/sdr_ctrl/trunk/verif
24	Clean Up	dinesha	4480d 12h	/sdr_ctrl/trunk/verif
22	Pad sdram clock added	dinesha	4481d 17h	/sdr_ctrl/trunk/verif
21	Clean up	dinesha	4481d 17h	/sdr_ctrl/trunk/verif
20	8 Bit SDARM support is added	dinesha	4483d 12h	/sdr_ctrl/trunk/verif
19	8 Bit SDRAM Support added	dinesha	4483d 12h	/sdr_ctrl/trunk/verif
18	8 Bit SDRAM Support is added	dinesha	4483d 12h	/sdr_ctrl/trunk/verif
17	micron 8 bit memory models are added into svn	dinesha	4483d 12h	/sdr_ctrl/trunk/verif
14	Unnecessary device config are removed	dinesha	4486d 13h	/sdr_ctrl/trunk/verif
12	Column Bits are made programmable	dinesha	4486d 13h	/sdr_ctrl/trunk/verif
10	Waveform files are added into SVN	dinesha	4489d 14h	/sdr_ctrl/trunk/verif
8	test bench files are added into SVN	dinesha	4490d 14h	/sdr_ctrl/trunk/verif
7	SDRAM Memory Models are added into SVN	dinesha	4490d 14h	/sdr_ctrl/trunk/verif
6	Golden Log files are added into SVN	dinesha	4490d 14h	/sdr_ctrl/trunk/verif
5	Run files are updated into SVN	dinesha	4490d 14h	/sdr_ctrl/trunk/verif
2		dinesha	4500d 14h	/sdr_ctrl/trunk/verif