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[/] [sdr_ctrl/] [trunk/] [verif] - Rev 30

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30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4480d 04h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4480d 04h /sdr_ctrl/trunk/verif
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4480d 04h /sdr_ctrl/trunk/verif
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4481d 02h /sdr_ctrl/trunk/verif
26 invalid log files are removed dinesha 4481d 03h /sdr_ctrl/trunk/verif
25 tb.sv is renamed as tb_top dinesha 4481d 03h /sdr_ctrl/trunk/verif
24 Clean Up dinesha 4481d 03h /sdr_ctrl/trunk/verif
22 Pad sdram clock added dinesha 4482d 08h /sdr_ctrl/trunk/verif
21 Clean up dinesha 4482d 08h /sdr_ctrl/trunk/verif
20 8 Bit SDARM support is added dinesha 4484d 03h /sdr_ctrl/trunk/verif
19 8 Bit SDRAM Support added dinesha 4484d 03h /sdr_ctrl/trunk/verif
18 8 Bit SDRAM Support is added dinesha 4484d 03h /sdr_ctrl/trunk/verif
17 micron 8 bit memory models are added into svn dinesha 4484d 03h /sdr_ctrl/trunk/verif
14 Unnecessary device config are removed dinesha 4487d 04h /sdr_ctrl/trunk/verif
12 Column Bits are made programmable dinesha 4487d 04h /sdr_ctrl/trunk/verif
10 Waveform files are added into SVN dinesha 4490d 05h /sdr_ctrl/trunk/verif
8 test bench files are added into SVN dinesha 4491d 05h /sdr_ctrl/trunk/verif
7 SDRAM Memory Models are added into SVN dinesha 4491d 05h /sdr_ctrl/trunk/verif
6 Golden Log files are added into SVN dinesha 4491d 05h /sdr_ctrl/trunk/verif
5 Run files are updated into SVN dinesha 4491d 05h /sdr_ctrl/trunk/verif

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