URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk] - Rev 12

Rev	Log message	Author	Age	Path
12	Column Bits are made programmable	dinesha	4515d 17h	/sdr_ctrl/trunk
11	SDRAM Specification document added into SVN	dinesha	4518d 18h	/sdr_ctrl/trunk
10	Waveform files are added into SVN	dinesha	4518d 18h	/sdr_ctrl/trunk
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4519d 18h	/sdr_ctrl/trunk
8	test bench files are added into SVN	dinesha	4519d 18h	/sdr_ctrl/trunk
7	SDRAM Memory Models are added into SVN	dinesha	4519d 18h	/sdr_ctrl/trunk
6	Golden Log files are added into SVN	dinesha	4519d 18h	/sdr_ctrl/trunk
5	Run files are updated into SVN	dinesha	4519d 18h	/sdr_ctrl/trunk
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4520d 15h	/sdr_ctrl/trunk
3	SDRAM controller core files are checked in	dinesha	4527d 01h	/sdr_ctrl/trunk
2		dinesha	4529d 18h	/sdr_ctrl/trunk
1	The project and the structure was created	root	4533d 17h	/sdr_ctrl/trunk