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[/] [sdr_ctrl/] [trunk] - Rev 15

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Rev Log message Author Age Path
15 Port cleanup dinesha 4706d 06h /sdr_ctrl/trunk
14 Unnecessary device config are removed dinesha 4706d 06h /sdr_ctrl/trunk
13 column bit are made progrmmable dinesha 4706d 07h /sdr_ctrl/trunk
12 Column Bits are made programmable dinesha 4706d 07h /sdr_ctrl/trunk
11 SDRAM Specification document added into SVN dinesha 4709d 08h /sdr_ctrl/trunk
10 Waveform files are added into SVN dinesha 4709d 08h /sdr_ctrl/trunk
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4710d 07h /sdr_ctrl/trunk
8 test bench files are added into SVN dinesha 4710d 07h /sdr_ctrl/trunk
7 SDRAM Memory Models are added into SVN dinesha 4710d 07h /sdr_ctrl/trunk
6 Golden Log files are added into SVN dinesha 4710d 08h /sdr_ctrl/trunk
5 Run files are updated into SVN dinesha 4710d 08h /sdr_ctrl/trunk
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4711d 05h /sdr_ctrl/trunk
3 SDRAM controller core files are checked in dinesha 4717d 15h /sdr_ctrl/trunk
2 dinesha 4720d 07h /sdr_ctrl/trunk
1 The project and the structure was created root 4724d 07h /sdr_ctrl/trunk

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