URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl] - Rev 17

Rev	Log message	Author	Age	Path
17	micron 8 bit memory models are added into svn	dinesha	4491d 02h	/sdr_ctrl
16	8 Bit SDRAM Support is added	dinesha	4491d 03h	/sdr_ctrl
15	Port cleanup	dinesha	4494d 03h	/sdr_ctrl
14	Unnecessary device config are removed	dinesha	4494d 03h	/sdr_ctrl
13	column bit are made progrmmable	dinesha	4494d 04h	/sdr_ctrl
12	Column Bits are made programmable	dinesha	4494d 04h	/sdr_ctrl
11	SDRAM Specification document added into SVN	dinesha	4497d 04h	/sdr_ctrl
10	Waveform files are added into SVN	dinesha	4497d 05h	/sdr_ctrl
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4498d 04h	/sdr_ctrl
8	test bench files are added into SVN	dinesha	4498d 04h	/sdr_ctrl
7	SDRAM Memory Models are added into SVN	dinesha	4498d 04h	/sdr_ctrl
6	Golden Log files are added into SVN	dinesha	4498d 04h	/sdr_ctrl
5	Run files are updated into SVN	dinesha	4498d 04h	/sdr_ctrl
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4499d 02h	/sdr_ctrl
3	SDRAM controller core files are checked in	dinesha	4505d 12h	/sdr_ctrl
2		dinesha	4508d 04h	/sdr_ctrl
1	The project and the structure was created	root	4512d 04h	/sdr_ctrl