URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl] - Rev 21

Rev	Log message	Author	Age	Path
21	Clean up	dinesha	4487d 20h	/sdr_ctrl
20	8 Bit SDARM support is added	dinesha	4489d 14h	/sdr_ctrl
19	8 Bit SDRAM Support added	dinesha	4489d 14h	/sdr_ctrl
18	8 Bit SDRAM Support is added	dinesha	4489d 14h	/sdr_ctrl
17	micron 8 bit memory models are added into svn	dinesha	4489d 15h	/sdr_ctrl
16	8 Bit SDRAM Support is added	dinesha	4489d 15h	/sdr_ctrl
15	Port cleanup	dinesha	4492d 15h	/sdr_ctrl
14	Unnecessary device config are removed	dinesha	4492d 15h	/sdr_ctrl
13	column bit are made progrmmable	dinesha	4492d 16h	/sdr_ctrl
12	Column Bits are made programmable	dinesha	4492d 16h	/sdr_ctrl
11	SDRAM Specification document added into SVN	dinesha	4495d 17h	/sdr_ctrl
10	Waveform files are added into SVN	dinesha	4495d 17h	/sdr_ctrl
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4496d 16h	/sdr_ctrl
8	test bench files are added into SVN	dinesha	4496d 16h	/sdr_ctrl
7	SDRAM Memory Models are added into SVN	dinesha	4496d 16h	/sdr_ctrl
6	Golden Log files are added into SVN	dinesha	4496d 17h	/sdr_ctrl
5	Run files are updated into SVN	dinesha	4496d 17h	/sdr_ctrl
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4497d 14h	/sdr_ctrl
3	SDRAM controller core files are checked in	dinesha	4504d 00h	/sdr_ctrl
2		dinesha	4506d 16h	/sdr_ctrl