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[/] [sdr_ctrl] - Rev 37

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Rev Log message Author Age Path
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4483d 23h /sdr_ctrl
36 Clean up dinesha 4484d 14h /sdr_ctrl
35 Updated the New Documents - ver 0.1 dinesha 4484d 16h /sdr_ctrl
34 Removed the older version dinesha 4484d 16h /sdr_ctrl
33 clean up dinesha 4484d 16h /sdr_ctrl
32 Debug is enable through +define dinesha 4486d 15h /sdr_ctrl
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4486d 15h /sdr_ctrl
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4486d 16h /sdr_ctrl
29 SDRAM top and core related run file list are added into svn dinesha 4486d 16h /sdr_ctrl
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4486d 16h /sdr_ctrl
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4487d 14h /sdr_ctrl
26 invalid log files are removed dinesha 4487d 14h /sdr_ctrl
25 tb.sv is renamed as tb_top dinesha 4487d 14h /sdr_ctrl
24 Clean Up dinesha 4487d 14h /sdr_ctrl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4488d 19h /sdr_ctrl
22 Pad sdram clock added dinesha 4488d 19h /sdr_ctrl
21 Clean up dinesha 4488d 19h /sdr_ctrl
20 8 Bit SDARM support is added dinesha 4490d 14h /sdr_ctrl
19 8 Bit SDRAM Support added dinesha 4490d 14h /sdr_ctrl
18 8 Bit SDRAM Support is added dinesha 4490d 14h /sdr_ctrl
17 micron 8 bit memory models are added into svn dinesha 4490d 14h /sdr_ctrl
16 8 Bit SDRAM Support is added dinesha 4490d 14h /sdr_ctrl
15 Port cleanup dinesha 4493d 15h /sdr_ctrl
14 Unnecessary device config are removed dinesha 4493d 15h /sdr_ctrl
13 column bit are made progrmmable dinesha 4493d 15h /sdr_ctrl
12 Column Bits are made programmable dinesha 4493d 15h /sdr_ctrl
11 SDRAM Specification document added into SVN dinesha 4496d 16h /sdr_ctrl
10 Waveform files are added into SVN dinesha 4496d 16h /sdr_ctrl
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4497d 16h /sdr_ctrl
8 test bench files are added into SVN dinesha 4497d 16h /sdr_ctrl

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