URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl] - Rev 59

Rev	Log message	Author	Age	Path
59	Control path request and data are register now for better FPGA timing	dinesha	4480d 16h	/sdr_ctrl
58	Read Data is register on RD_FAST=0 case	dinesha	4480d 16h	/sdr_ctrl
57	Synthesis constraints are added	dinesha	4481d 06h	/sdr_ctrl
56	FPGA Synth optimisation	dinesha	4481d 07h	/sdr_ctrl
55	FPGA Synthesis timing optimisation	dinesha	4481d 07h	/sdr_ctrl
54	FPGA Timing Optimisation	dinesha	4484d 05h	/sdr_ctrl
53	Test bench upgradation	dinesha	4485d 05h	/sdr_ctrl
52	Documentation update for request control and transfer control block	dinesha	4485d 06h	/sdr_ctrl
51	FPGA relating timing optimisation done	dinesha	4485d 06h	/sdr_ctrl
50	Bug fix the request length is fixe	dinesha	4487d 10h	/sdr_ctrl
49	clean up	dinesha	4488d 09h	/sdr_ctrl
48	top-level cleanup	dinesha	4488d 09h	/sdr_ctrl
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4488d 09h	/sdr_ctrl
46	test bench upgrade + rtl cleanup	dinesha	4490d 10h	/sdr_ctrl
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4490d 14h	/sdr_ctrl
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4492d 12h	/sdr_ctrl
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4492d 14h	/sdr_ctrl
42	Bug fix in read access is fixed	dinesha	4492d 14h	/sdr_ctrl
41	Updated Spec ver 0.1 is added back to svn	dinesha	4492d 15h	/sdr_ctrl
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4493d 08h	/sdr_ctrl