URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 30

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4480d 08h	/
29	SDRAM top and core related run file list are added into svn	dinesha	4480d 08h	/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4480d 08h	/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4481d 06h	/
26	invalid log files are removed	dinesha	4481d 06h	/
25	tb.sv is renamed as tb_top	dinesha	4481d 06h	/
24	Clean Up	dinesha	4481d 06h	/
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4482d 12h	/
22	Pad sdram clock added	dinesha	4482d 12h	/
21	Clean up	dinesha	4482d 12h	/
20	8 Bit SDARM support is added	dinesha	4484d 06h	/
19	8 Bit SDRAM Support added	dinesha	4484d 06h	/
18	8 Bit SDRAM Support is added	dinesha	4484d 06h	/
17	micron 8 bit memory models are added into svn	dinesha	4484d 07h	/
16	8 Bit SDRAM Support is added	dinesha	4484d 07h	/
15	Port cleanup	dinesha	4487d 07h	/
14	Unnecessary device config are removed	dinesha	4487d 07h	/
13	column bit are made progrmmable	dinesha	4487d 08h	/
12	Column Bits are made programmable	dinesha	4487d 08h	/
11	SDRAM Specification document added into SVN	dinesha	4490d 09h	/