OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 41

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
41 Updated Spec ver 0.1 is added back to svn dinesha 4494d 16h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4495d 09h /
39 Test Bench upgradation with bigger data burst size dinesha 4495d 09h /
38 Port Name clean up dinesha 4496d 14h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4496d 16h /
36 Clean up dinesha 4497d 07h /
35 Updated the New Documents - ver 0.1 dinesha 4497d 09h /
34 Removed the older version dinesha 4497d 09h /
33 clean up dinesha 4497d 09h /
32 Debug is enable through +define dinesha 4499d 08h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4499d 08h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4499d 08h /
29 SDRAM top and core related run file list are added into svn dinesha 4499d 08h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4499d 08h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4500d 06h /
26 invalid log files are removed dinesha 4500d 07h /
25 tb.sv is renamed as tb_top dinesha 4500d 07h /
24 Clean Up dinesha 4500d 07h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4501d 12h /
22 Pad sdram clock added dinesha 4501d 12h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.