OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 42

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
42 Bug fix in read access is fixed dinesha 4473d 01h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4473d 02h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4473d 19h /
39 Test Bench upgradation with bigger data burst size dinesha 4473d 19h /
38 Port Name clean up dinesha 4475d 00h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4475d 02h /
36 Clean up dinesha 4475d 17h /
35 Updated the New Documents - ver 0.1 dinesha 4475d 19h /
34 Removed the older version dinesha 4475d 19h /
33 clean up dinesha 4475d 19h /
32 Debug is enable through +define dinesha 4477d 18h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4477d 18h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4477d 18h /
29 SDRAM top and core related run file list are added into svn dinesha 4477d 18h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4477d 18h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4478d 16h /
26 invalid log files are removed dinesha 4478d 17h /
25 tb.sv is renamed as tb_top dinesha 4478d 17h /
24 Clean Up dinesha 4478d 17h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4479d 22h /
22 Pad sdram clock added dinesha 4479d 22h /
21 Clean up dinesha 4479d 22h /
20 8 Bit SDARM support is added dinesha 4481d 17h /
19 8 Bit SDRAM Support added dinesha 4481d 17h /
18 8 Bit SDRAM Support is added dinesha 4481d 17h /
17 micron 8 bit memory models are added into svn dinesha 4481d 17h /
16 8 Bit SDRAM Support is added dinesha 4481d 17h /
15 Port cleanup dinesha 4484d 18h /
14 Unnecessary device config are removed dinesha 4484d 18h /
13 column bit are made progrmmable dinesha 4484d 18h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.