Subversion Repositories sdr_ctrl

[/] - Rev 43


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4523d 04h /
42 Bug fix in read access is fixed dinesha 4523d 04h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4523d 06h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4523d 23h /
39 Test Bench upgradation with bigger data burst size dinesha 4523d 23h /
38 Port Name clean up dinesha 4525d 04h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4525d 06h /
36 Clean up dinesha 4525d 20h /
35 Updated the New Documents - ver 0.1 dinesha 4525d 22h /
34 Removed the older version dinesha 4525d 22h /
33 clean up dinesha 4525d 23h /
32 Debug is enable through +define dinesha 4527d 21h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4527d 21h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4527d 22h /
29 SDRAM top and core related run file list are added into svn dinesha 4527d 22h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4527d 22h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4528d 20h /
26 invalid log files are removed dinesha 4528d 20h /
25 is renamed as tb_top dinesha 4528d 20h /
24 Clean Up dinesha 4528d 20h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.