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Rev Log message Author Age Path
63 FPGA Bench mark results are added dinesha 4487d 21h /
62 Synthesis constraint for simplify dinesha 4487d 21h /
61 RTL file list are added into SVN dinesha 4487d 22h /
60 warning cleanup dinesha 4487d 22h /
59 Control path request and data are register now for better FPGA timing dinesha 4487d 22h /
58 Read Data is register on RD_FAST=0 case dinesha 4487d 22h /
57 Synthesis constraints are added dinesha 4488d 13h /
56 FPGA Synth optimisation dinesha 4488d 14h /
55 FPGA Synthesis timing optimisation dinesha 4488d 14h /
54 FPGA Timing Optimisation dinesha 4491d 12h /
53 Test bench upgradation dinesha 4492d 12h /
52 Documentation update for request control and transfer control block dinesha 4492d 12h /
51 FPGA relating timing optimisation done dinesha 4492d 12h /
50 Bug fix the request length is fixe dinesha 4494d 16h /
49 clean up dinesha 4495d 15h /
48 top-level cleanup dinesha 4495d 15h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4495d 15h /
46 test bench upgrade + rtl cleanup dinesha 4497d 16h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4497d 20h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4499d 19h /

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