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Subversion Repositories sdr_ctrl

[/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 351d 05h /
72 Command Clean up for model-sim mode dinesha 3344d 14h /
71 Warning cleanup dinesha 3396d 06h /
70 Warning Cleanup dinesha 3396d 06h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 3396d 07h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 3396d 07h /
67 time scale removed dinesha 3466d 05h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 3714d 06h /
65 Updated Log file with CAS latency support 4,5 dinesha 3714d 14h /
64 CAS Latency support added for 4,5 dinesha 3714d 14h /
63 FPGA Bench mark results are added dinesha 3833d 13h /
62 Synthesis constraint for simplify dinesha 3833d 13h /
61 RTL file list are added into SVN dinesha 3833d 14h /
60 warning cleanup dinesha 3833d 14h /
59 Control path request and data are register now for better FPGA timing dinesha 3833d 14h /
58 Read Data is register on RD_FAST=0 case dinesha 3833d 14h /
57 Synthesis constraints are added dinesha 3834d 04h /
56 FPGA Synth optimisation dinesha 3834d 05h /
55 FPGA Synthesis timing optimisation dinesha 3834d 06h /
54 FPGA Timing Optimisation dinesha 3837d 03h /

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