URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [sha256.gise] - Rev 10

Rev	Log message	Author	Age	Path
10	Optimized control logic; Reduced one clock cycle for full last blocks, eliminated sch_ld redundant logic. Improved error detection logic, eliminating the bytes error register. Updated testbench with write violations and full block corner case tests.	jdoin	2770d 14h	/sha256_hash_core/trunk/syn/sha256/sha256.gise
7	Delete intermediate files from repository. All commits are done after a Project/Cleanup.	jdoin	2858d 02h	/sha256_hash_core/trunk/syn/sha256/sha256.gise
6	Added Sim_test_1.png and Sim_test_8.png simulation pictures. Changed testbench for faster data input. Changed License text on all files. Consolidated file header info.	jdoin	2858d 02h	/sha256_hash_core/trunk/syn/sha256/sha256.gise
3	Added GV_SHA256 block logic schematics.	jdoin	2859d 08h	/sha256_hash_core/trunk/syn/sha256/sha256.gise
2	SHA256 RTL code simulated and verified, to all NIST verification vectors. Pre-par synthesis show 74MHz clock rate, with no pipelining.	jdoin	2859d 10h	/sha256_hash_core/trunk/syn/sha256/sha256.gise