URL https://opencores.org/ocsvn/simpcon/simpcon/trunk

Subversion Repositories simpcon

[/] - Rev 30

Rev	Log message	Author	Age	Path
30	Update to V1.1	martin	5463d 23h	/
29	New and changed VHDL example files	martin	5464d 00h	/
28	Added old uploaded documents to new repository.	root	5547d 02h	/
27	Added old uploaded documents to new repository.	root	5547d 08h	/
26	New directory structure.	root	5547d 08h	/
25	clearification of simple read timing	martin	6029d 23h	/
24	remived JOP library references	martin	6083d 23h	/
23	no message	martin	6086d 01h	/
22	update with Austrochip paper content and VHDL file descriptions	martin	6090d 14h	/
21	VHDL update	martin	6090d 14h	/
20	VHDL update	martin	6090d 17h	/
19	moved to JOP handbook	martin	6090d 17h	/
18	update from JOP	martin	6263d 16h	/
17	SimpCon - Wishbone bridge	martin	6714d 00h	/
16	Minimum SimpCon IO example	martin	6714d 00h	/
15	ISA bus example (used to connect the CS8900 Ethernet chip)	martin	6714d 00h	/
14	renamed to scio_min.vhd	martin	6714d 00h	/
13	no message	martin	6723d 04h	/
12	more IO examples	martin	6737d 03h	/
11	no message	martin	6737d 03h	/
10	Removed Flash ports	martin	6741d 19h	/
9	Generic decoding and data mux	martin	6743d 05h	/
8	Test IO slave and simple IO top	martin	6743d 07h	/
7	Changed signal names to use the names from the specification.	martin	6744d 23h	/
6	Signal section added	martin	6745d 02h	/
5	Add document sources to the project	martin	6745d 02h	/
4	A 32-bis static RAM slave with read pipeline level 2	martin	6745d 09h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		6745d 09h	/
2	no message	martin	6745d 09h	/
1	Standard project directories initialized by cvs2svn.		6745d 09h	/