URL https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk

Subversion Repositories simple_fm_receiver

[/] [simple_fm_receiver/] [trunk] - Rev 32

Rev	Log message	Author	Age	Path
32	New directory structure.	root	5551d 22h	/simple_fm_receiver/trunk
31	Include flattening process, simplify build system.	arif_endro	5763d 22h	/trunk
30	Clean up.	arif_endro	5808d 03h	/trunk
29	Done fixing Makefile for Alliance.	arif_endro	5808d 03h	/trunk
28	chip IO place.	arif_endro	5808d 23h	/trunk
27	chip IO interface.	arif_endro	5808d 23h	/trunk
26	Removed.	arif_endro	5808d 23h	/trunk
25	IO place.	arif_endro	5808d 23h	/trunk
24	Update to use Alliance CAD System by ASIM/LIP6/UMPC	arif_endro	5809d 01h	/trunk
23	Disable clear signal.	arif_endro	5809d 01h	/trunk
22	Update last bit output assignment method.	arif_endro	5809d 01h	/trunk
20	New Version	arif_endro	6994d 02h	/trunk
19	Screen shot from chipscope analyzer view, this is how this design work.	arif_endro	7000d 01h	/trunk
18	This bit files generates better wave than previous (i.e. more smooth)	arif_endro	7000d 03h	/trunk
17	Initial Checkin	arif_endro	7008d 00h	/trunk
16	Changes constan and minor fix	arif_endro	7011d 03h	/trunk
15	Xilinx FPGA XC2V2000 bit files the first version.	arif_endro	7014d 01h	/trunk
14	* empty log message *	arif_endro	7018d 23h	/trunk
13	Update License	arif_endro	7030d 00h	/trunk
12	Update License Change reset signal handle	arif_endro	7030d 01h	/trunk