URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [ram_wb/] [ram_wb.yaml] - Rev 10

Rev	Log message	Author	Age	Path
10	replaced version by id for cores and interfaces	feddischson	3562d 13h	/soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml
8	Further improvments: e.g. added default and mandatory option for ports. Commit before some cleaning	feddischson	3562d 13h	/soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml
7	First revision, which produces a synthesizable (simple) SOC	feddischson	3562d 13h	/soc_maker/trunk/core_lib/cores/ram_wb/ram_wb.yaml