URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] - Rev 23

Rev	Log message	Author	Age	Path
23	FPGA verilog and corrections.	redbear	2571d 21h	/spacewiresystemc/
22	Adding files work to altera fpga DE0 NANO SOC.	redbear	2571d 21h	/spacewiresystemc/
21	Vpi data rx.	redbear	2592d 20h	/spacewiresystemc/
20	SystemC minor correction.	redbear	2592d 20h	/spacewiresystemc/
19	RX and TX correct.	redbear	2592d 20h	/spacewiresystemc/
18	FSM minor correction	redbear	2599d 19h	/spacewiresystemc/
17	TX correction FCT reaceive and TX data transfer.	redbear	2599d 19h	/spacewiresystemc/
16	Adding TX_WRITE to go down after detect first edge posedge tx_ready.	redbear	2599d 19h	/spacewiresystemc/
15	Tx with FCT with partial correction.	redbear	2627d 20h	/spacewiresystemc/
14	New version of Receiver.	redbear	2627d 20h	/spacewiresystemc/
13	upating files.	redbear	2654d 21h	/spacewiresystemc/
12	update files and SystemC.	redbear	2676d 21h	/spacewiresystemc/
11	Adding shared object.	redbear	2686d 21h	/spacewiresystemc/
10	Update tx verilog rx systemc test.	redbear	2686d 21h	/spacewiresystemc/
9	Update shared object and Graphical interface.	redbear	2686d 21h	/spacewiresystemc/
8	EOPDATA is functional.	redbear	2686d 22h	/spacewiresystemc/
7	Updating testbench file using correcting signals VPI.	redbear	2691d 23h	/spacewiresystemc/
6	Updating FCT and NCHAR counters on TX.	redbear	2691d 23h	/spacewiresystemc/
5	Adding first verilog with new struct dir.	redbear	2703d 22h	/spacewiresystemc/
4	Deleting all	redbear	2703d 22h	/spacewiresystemc/