OpenCores
URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [tags/] [rx_beta_1/] - Rev 73

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 New directory structure. root 5556d 21h /spdif_interface/tags/rx_beta_1/
43 This commit was manufactured by cvs2svn to create tag 'rx_beta_1'. 7258d 13h /tags/rx_beta_1/
42 Fixed bug with lock event generation. gedra 7258d 13h /trunk/
41 Test bench update. gedra 7258d 13h /trunk/
40 Improved test bench. gedra 7259d 14h /trunk/
39 Bug-fix. gedra 7259d 14h /trunk/
38 Signal renaming and bug fix. gedra 7273d 14h /trunk/
37 Converted to numeric_std and fixed a few bugs. gedra 7274d 16h /trunk/
36 Top level entity for receiver. gedra 7274d 16h /trunk/
35 Top level test bench for receiver. NB! Not complete. gedra 7274d 16h /trunk/
34 Converter to numeric_std and added hex functions gedra 7274d 16h /trunk/
33 Minor update. gedra 7274d 16h /trunk/
32 Wishbone bus utilities. gedra 7276d 11h /trunk/
31 Added data output. gedra 7276d 11h /trunk/
30 Added Wishbone bus cycle decoder. gedra 7277d 12h /trunk/
29 Wishbone bus cycle decoder. gedra 7277d 12h /trunk/
28 Delint'ed and changed name of architecture. gedra 7281d 20h /trunk/
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7282d 11h /trunk/
26 Fixed a few bugs. gedra 7284d 11h /trunk/
25 Changed status reg. declaration gedra 7284d 11h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.