| Rev |
Log message |
Author |
Age |
Path |
| 25 |
|
jdoin |
4744d 04h |
/spi_master_slave/trunk/ |
| 24 |
- fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk |
jdoin |
4744d 04h |
/spi_master_slave/trunk/ |
| 23 |
Clarified copyright and licensing
Added trunk/license directory
Added LGPL 3.0 license text "lgpl.txt"
Fixed inline url for the GNU link of the LGPL license
Updated readme files and rtl files |
jdoin |
4764d 08h |
/spi_master_slave/trunk/ |
| 22 |
spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. |
jdoin |
4765d 19h |
/spi_master_slave/trunk/ |
| 21 |
- Updated ISE13 verification project. |
jdoin |
4782d 22h |
/spi_master_slave/trunk/ |
| 20 |
- removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores. |
jdoin |
4783d 21h |
/spi_master_slave/trunk/ |
| 19 |
v2.02.0123: ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, the slave will send (others => '0') instead. |
jdoin |
4785d 20h |
/spi_master_slave/trunk/ |
| 18 |
v2.02.0122: Fixed bug SLAVE Continuous Transfer.
The fix consists in engaging continuous transfer regardless of the user strobing write enable, and sequencing from state 1 to N as long as the master clock is present.
If the user does not write new data, the last data word is repeated. |
jdoin |
4786d 03h |
/spi_master_slave/trunk/ |
| 17 |
Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. |
jdoin |
4789d 18h |
/spi_master_slave/trunk/ |
| 16 |
Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. |
jdoin |
4789d 18h |
/spi_master_slave/trunk/ |
| 15 |
Updated manual text. |
jdoin |
4790d 23h |
/spi_master_slave/trunk/ |
| 14 |
Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code. |
jdoin |
4791d 22h |
/spi_master_slave/trunk/ |
| 13 |
spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135
Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers. |
jdoin |
4792d 18h |
/spi_master_slave/trunk/ |
| 12 |
SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks. |
jdoin |
4796d 18h |
/spi_master_slave/trunk/ |
| 11 |
v1.12.0105: Modified SCK output circuit in spi_master.vhd.
In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz. |
jdoin |
4807d 17h |
/spi_master_slave/trunk/ |
| 10 |
v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise. |
jdoin |
4808d 18h |
/spi_master_slave/trunk/ |
| 9 |
Updated verification data. |
jdoin |
4812d 06h |
/spi_master_slave/trunk/ |
| 8 |
Updated Documentation |
jdoin |
4812d 06h |
/spi_master_slave/trunk/ |
| 7 |
Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. |
jdoin |
4812d 20h |
/spi_master_slave/trunk/ |
| 6 |
v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
4814d 17h |
/spi_master_slave/trunk/ |
