URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [doc/] [src/] [spi_master_slave_Specifications.doc] - Rev 14

Rev	Log message	Author	Age	Path
14	Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code.	jdoin	4650d 05h	/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
7	Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual.	jdoin	4671d 03h	/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
5	Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing. Added SPI line clock divider from high-speed system clock. Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies. Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.	jdoin	4673d 01h	/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
4	v0.97.0068 - streamlined resets and clock enables to reduce area v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit v0.97.0086 - removed master MISO input register: got 33MHz.	jdoin	4698d 01h	/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc
2	v0.95.0050 - Master/Slave loopback verified at 25MHz.	jdoin	4715d 04h	/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc