| Rev |
Log message |
Author |
Age |
Path |
| 24 |
- fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk |
jdoin |
4994d 07h |
/spi_master_slave/trunk/syn/ |
| 23 |
Clarified copyright and licensing
Added trunk/license directory
Added LGPL 3.0 license text "lgpl.txt"
Fixed inline url for the GNU link of the LGPL license
Updated readme files and rtl files |
jdoin |
5014d 11h |
/spi_master_slave/trunk/syn/ |
| 22 |
spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. |
jdoin |
5015d 22h |
/spi_master_slave/trunk/syn/ |
| 21 |
- Updated ISE13 verification project. |
jdoin |
5033d 01h |
/spi_master_slave/trunk/syn/ |
| 20 |
- removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores. |
jdoin |
5034d 00h |
/spi_master_slave/trunk/syn/ |
| 19 |
v2.02.0123: ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, the slave will send (others => '0') instead. |
jdoin |
5035d 23h |
/spi_master_slave/trunk/syn/ |
| 18 |
v2.02.0122: Fixed bug SLAVE Continuous Transfer.
The fix consists in engaging continuous transfer regardless of the user strobing write enable, and sequencing from state 1 to N as long as the master clock is present.
If the user does not write new data, the last data word is repeated. |
jdoin |
5036d 06h |
/spi_master_slave/trunk/syn/ |
| 17 |
Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. |
jdoin |
5039d 21h |
/spi_master_slave/trunk/syn/ |
| 16 |
Master: v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
Slave: v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. |
jdoin |
5039d 22h |
/spi_master_slave/trunk/syn/ |
| 14 |
Updated specifications manual, deleted old documentation stuff, changed minor text errors in the code. |
jdoin |
5042d 01h |
/spi_master_slave/trunk/syn/ |
| 13 |
spi_slave.vhd: v2.02.0120
spi_master.vhd: v1.15.0135
Several bugs fixed. Master and Slave cores tested at all spi modes, at 50MHz SCK, including continuous transfers. |
jdoin |
5042d 21h |
/spi_master_slave/trunk/syn/ |
| 12 |
SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks. |
jdoin |
5046d 21h |
/spi_master_slave/trunk/syn/ |
| 11 |
v1.12.0105: Modified SCK output circuit in spi_master.vhd.
In CPHA='0', top speed is +50MHz, in CPHA='1', top speed is 25MHz. |
jdoin |
5057d 20h |
/spi_master_slave/trunk/syn/ |
| 10 |
v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise. |
jdoin |
5058d 21h |
/spi_master_slave/trunk/syn/ |
| 9 |
Updated verification data. |
jdoin |
5062d 10h |
/spi_master_slave/trunk/syn/ |
| 7 |
Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. |
jdoin |
5062d 23h |
/spi_master_slave/trunk/syn/ |
| 6 |
v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
5064d 20h |
/spi_master_slave/trunk/syn/ |
| 5 |
Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation. |
jdoin |
5064d 20h |
/spi_master_slave/trunk/syn/ |
