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[/] [spi_master_slave/] [trunk/] [syn/] [ATLYS_01.SET] - Rev 5

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Rev Log message Author Age Path
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3315d 15h /spi_master_slave/trunk/syn/ATLYS_01.SET

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